Status and application of HgCdTe device modeling

In this article, device modeling refers to numerical simulation of semiconductor device physics to predict electrical behavior. The silicon integrated circuit industry provides the example for the use of technology computer-aided design to simulate wafer fabrication processes, and the electrical performance of devices and circuits. This paper first reviews semiconductor device modeling in general, then as applied in work supporting the development and analysis of HgCdTe infrared detectors. Example applications of one- and two-dimensional device modeling are simulation of a bias-selectable, integrated two-color detector, and two-dimensional effects on the spectral response of a HgCdTe detector with composition grading.     

Room temperature characterization of Hg1-xCdxTe P-on-n heterostructure photodiodes

Measurements of 77K R_oA and 300K reverse bias dynamic impedance (R_dA) products at one volt reverse bias has been carried out to assess the degree of correlation of this figure of merit. Planar P-on-n heterostructures were grown on near lattice-matched CdZnTe substrates with Hg_1-xCd_xTe (0.20< x <0.30) by molecular beam epitaxy. These devices were passivated with CdTe and doped with indium and arsenic as n- and p-type dopants, respectively. Current-voltage characteristic of these devices exhibit thermally generated dark currents at small and modest reverse bias. We have observed that R_oA values of these long wavelength infrared P-on-n heterostructure photodiodes at 77K correlate with room temperature R_dA values. Diode arrays with high room temperature R_dA values at one volt reverse bias also have high R_oA values at 77K. Similarly, low R_dA values at room temperature indicate poor performance at 77K where deviation from diffusion current occurs at reverse bias of 0.2 to 1 volt at room temperature. The results presented here, for a small samples of devices, demonstrate that room temperature measurements of current-voltage characteristics to evaluate Hg_1-xCd_xTe (0.22< x <0.28) diode performance and array uniformity at lower temperatures can be used. This provides an acceptable criteria for further study at lower temperatures.     

光导器件及其背景限探测度

本文就ＭＣＴ光导型探测器作一总结性的讨论，对光导器件的扫出问题作了更详尽的阐述，并定义了扫出因子。关于背景限探测度提出了新的见解，认为背景限探测度不是不可逾越。     

p型碲镉汞液相外延材料Ag掺杂的研究

利用SIMS和变温霍尔测量手段对P型Hg0.77Gd0.23Te液相外延材料的Ag掺杂技术、机理及掺杂碲镉汞材料的性能进行了研究。结果表明采用AgNO3溶液直接浸泡方式对该材料进行掺Ag是成功的，掺杂浓度与被掺杂材料中的汞空位浓度是一致的，掺杂后，P型碲镉汞材料的受主能级比掺杂前有明显的减小，从实验结果可看到掺Ag碲镉汞材料的电学性能在室温下保持稳定。     

分子束外延生长3英寸HgCdTe晶片

报道了用分子束外延的方法制备3英寸HgCdTe薄膜的研究结果,获得的HgCdTe外延材料均匀性良好,在直径70mm圆内,组份标准偏差率为1.2%,对应80K截止波长偏差仅为0.1μm.经过生长条件的改进,表面形貌获得了大幅度改善,缺陷密刃∮00cm-2,缺陷尺寸小于10μm,可以满足大规模HgCdTe焦平面列阵的应用需求.抖     

A study on surface polishing of SiC with a tribochemical reaction mechanism

This work investigates the surface polishing of silicon carbide SiC using the tribochemical reaction mechanism. Different metal discs – cast iron, AISI 304 stainless steel, S45C medium carbon steel plated chromium, brass and copper – are used to polish SiC in water and kerosene, respectively. The experimental results show that ferrous metal discs can effectively polish SiC in water. Also, no surface damage or scratches on the polished surface of SiC are observed by this method. The polishing debris was analyzed by electron spectroscopy for chemical analysis. The analyzed results indicate that the polishing surface of SiC is removed tribochemically with the aid of catalytic effect of iron oxide. Moreover, in this process the maximum material removal rate is about 0.06 m/h.     

CdTe/ZnS双层钝化碲镉汞长波探测器制备的研究

开展了CdTe/ZnS双层钝化碲镉汞长波探测器制备的研究。CdTe钝化膜经退火热处理后,可实现CdTe/MCT界面的互扩散,并改善CdTe钝化膜的质量。通过全湿法腐蚀方法完成了金属化开口,制备了长波碲镉汞600×18@15 μm规格线列和640×512@15 μm规格面阵。线列I-V测试表明:CdTe/ZnS双层钝化膜能有效地减少长波碲镉汞器件的表面漏电流,器件的反向结特性良好。面阵在77K测试:NETD 26.7 mK,有效像元率95.4%,并对室温目标进行了凝视成像。测试过程出现了4%左右由噪声引起的零散盲元,是由芯片面阵局部钝化失效引起的,表明钝化膜沉积工艺及芯片加工工艺尚有改进的空间。     

原位As掺杂p型碲镉汞薄膜的制备研究

非本征p 型掺杂碲镉汞材料可以有效克服少子寿命偏低等问题,提高长波和甚长波红外焦平面器件的性能。本文重点阐述了As 掺杂实现p型掺杂的基础性原理,以及其制备方法,为p-on-n碲镉汞材料器件研究提供依据。     

HgCdTe光伏器件多层钝化膜等离子体处理的研究

在HgCdT e光伏探测器件S iO2+ZnS复合介质膜钝化中,引入O+2清洗和A+r刻蚀两种等离子体处理工艺,大大提高薄膜附着力,成功制备出优良的光伏器件。对处理前后的样品进行场发射扫描电子显微镜扫描、原子力显微镜扫描和二次离子质谱测试后发现,O+2清洗对去除样品表面的残余光刻胶效果显著;而A r+刻蚀使ZnS表面更为粗糙,增加了成核中心,使S iO2和ZnS表面互相渗透,增强了两层介质膜的附着力。     

HgCdTe器件中pn结结区扩展的表征方法

报道了液氮温度下激光束诱导电流(LBIC)和I-V测试两种在HgCdTe器件中pn结结区扩展的表征方法.通过LBIC和I-V测试,发现了p型HgCdTe材料中由B+离子注入成结和干法刻蚀成结对材料造成的损伤使得有效结区范围大于注入和刻蚀面积,并获得n区横向扩展.同时,通过对比,相互印证两种方法得到的测试结果一致.